Complementary MOS integrated circuit including lock-up prevention parasitic transistors

US4689653A · kind A · utility

Assignee

• Mitsubishi Electric Corporation · JP

Inventor

• Yukio Miyazaki · Itami, JP

Key dates

• Filing date: Aug 26, 1985
• Grant date: Aug 25, 1987
• Expiry date: Aug 26, 2005

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/854

Abstract

In a complementary MOS-IC (CMOSIC) comprising a p-channel MOS transistor with an n-channel MOS transistor serially connected thereto, a third diffusion layer is provided being of a conductivity type similar to that of the drains of the respective transistors. This third diffusion layer produces a plurality of parasitic bipolar transistors which limit the gain of the naturally occurring parasitic transistors in the CMOSIC. By limiting the gain, the third diffusion layer drastically reduces the chance of CMOSIC breakdown upon the occurence of high input transients.