Memory with improved write mode to read mode transition
US4689771A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1986 |
| Grant date | Aug 25, 1987 |
| Priority date | — |
| Expiry date | Mar 3, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has a read mode in which data is read from a bit line pair selected by a column address and a write mode in which data is written onto a selected bit line pair. The selected bit line pair is coupled to a data line pair via a column decoder in response to a column address. Upon a transition from the write mode to the read mode the column decoder is disabled from coupling the selected data line to the data line pair for the duration of a column disable pulse. The column disable pulse is generated in response to a write transition pulse or a column transition pulse or both. The column transition pulse is generated in response to a change in the column address. The write transition pulse is generated in response to a write to read transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.