Multiple chip interconnection system and package
US4692839A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1985 |
| Grant date | Sep 8, 1987 |
| Priority date | — |
| Expiry date | Jun 24, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multiple chip interconnection system and package for interconnecting and cooling integrated circuits includes an electrically-conductive plate 10 having an upper surface 12. On the upper surface 12, a first layer of polyimide 16 or other electrically-insulating material is deposited. One or more layers of electrical interconnections 17, 18, 21, 22, and insulating material 19, 24, are then disposed on the insulating material 16 to provide a network of electrical connections embedded in insulating material, yet which is sufficiently thin to offer minimal thermal resistance to the transfer of heat from integrated circuits mounted thereon to the plate 10. After the layers of interconnections are completed, one or more conductive planes are deposited across the interconnections to serve as a mounting surface for the integrated circuits and to distribute power and ground signals as necessary. One or more integrated circuits 40 are then attached to the plane 32 and suitable interconnections made between the integrated circuits and desired regions 34 of the plane. The package is completed by attaching an air- or water-cooled heat sink 54 to the opposite side of plate 10 from the integrat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.