Process for fabricating semiconductor components
US4692998A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 1985 |
| Grant date | Sep 15, 1987 |
| Priority date | — |
| Expiry date | Jan 12, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for the fabrication of semiconductor components and in particular a process in which the components are fabricated with a controlled spacing of etched channels. The process is in particular utilized in fabricating a monolithic array of elements such as a pin diode array. The process of the present invention combines the use of an anisotropic silicon etching process for the desired device geometries with a means of defining all device surface topology by substantially a single photomask thus eliminating critical mask alignment. A second embodiment of the invention is also described employing fewer layers of deposition with a double photomask step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.