Sample-and-hold circuit
US4694341A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1986 |
| Grant date | Sep 15, 1987 |
| Priority date | — |
| Expiry date | Feb 4, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sample-and-hold circuit is provided wherein an input signal is fed via a first gate element to one end of a first capacitor whose other end is alternately grounded, the one end of the first capacitor being connected via a second capacitor to a gate (or base) of a source (or emitter) follower transistor to obtain an output from the source (or emitter) of the transistor which is connected via a second gate element to one end of the first capacitor, while the gate (or base) of the transistor is connected via a third gate element to a DC voltage supply having a predetermined voltage value, and the second and third gate elements are turned on during a first period of the input signal so that a voltage corresponding to the gate-source (or base-emitter) offset voltage of the transistor is stored in the second capacitor, while the first gate element is turned on during a second period of the input signal to produce an output signal equivalent in level to the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.