Clock adjustment method and apparatus for synchronous data communications
US4694472A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 2, 1984 |
| Grant date | Sep 15, 1987 |
| Priority date | — |
| Expiry date | Mar 2, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The disclosed clock adjustment method and apparatus utilizes a periodically transmitted positive or negative predetermined fixed increment clock phase adjustment signal to phase adjust the clocks of the system. The transmitter clock is periodically compared with a common reference clock and a fixed increment clock adjustment signal is transmitted to the receiver which adjusts its clock by applying the fixed increment clock adjustment signal to the common reference clock. The utilization of a predetermined fixed increment clock phase adjustment signal eliminates the need to send the resolution of the clock adjustment and hence reduces the number of data bits required to send clock information over the communication channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.