Fast two-level dynamic address translation method and means
US4695950A · kind A · utility
46Cited by
8References
10Claims
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Assignee
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Key dates
| Filing date | Sep 17, 1984 |
| Grant date | Sep 22, 1987 |
| Priority date | — |
| Expiry date | Sep 17, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A unique high-speed hardware arrangement for generating double-level address translations in combination a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.