Method of generating test patterns for logic network devices
US4696006A · kind A · utility
11Cited by
8References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 25, 1985 |
| Grant date | Sep 22, 1987 |
| Priority date | — |
| Expiry date | Nov 25, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318392
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Nodes and paths for connecting the nodes are used to form a model of at least one logic network. Next, all paths for connecting nodes in the logic network are traced, and the nodes and connecting path segments are sensitized and justified. The sensitizing patterns, when generating test patterns for a sequential circuit wherein the output is a function of a time sequence of inputs, may include a time sequence of sensitizing or input patterns for testing a single path through the network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.