Fluctuation-free input buffer
US4697110A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 1983 |
| Grant date | Sep 29, 1987 |
| Priority date | — |
| Expiry date | Nov 28, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018535
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input buffer for a semiconductor circuit is provided with a source follower circuit composed of a first FET whose gate electrode has an input connected thereto, and a second FET of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET directly or through at least one level-shifting diode and whose gate electrode is supplied with a control voltage. The input buffer also includes a FET inverter circuit connected to the drain electrode of the second FET directly or through at least one level-shifting diode. An output signal for the input buffer is derived from the FET inverter circuit. A particular advantage of the present invention is that it permits the input buffer to switch its output from one level to another in response to input signals falling within a predetermined voltage range regardless of logic threshold level fluctuations in the FETs and fluctuations in supply voltages coupled to the input buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.