Buffered Miller current compensating circuit
US4698525A · kind A · utility
16Cited by
5References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1985 |
| Grant date | Oct 6, 1987 |
| Priority date | — |
| Expiry date | Dec 3, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A TTL inverting output circuit (50) which uses the collector (65) of a parallel phase splitter transistor (Q11) where the voltage changes in phase with the circuit output signal Io to control an active circuit (70) which diverts charge from the base (23) of the output pull-down transistor (Q3).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.