FET with Fermi level pinning between channel and heavily doped semiconductor gate
US4698652A · kind A · utility
19Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 1985 |
| Grant date | Oct 6, 1987 |
| Priority date | — |
| Expiry date | May 8, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/097
Abstract
Herein disclosed is a semiconductor device in which control means for carriers migrating in a first semiconductor includes an interface state layer lying on the first semiconductor and a second conductor layer lying on the interface state layer. The interface state layer has its Fermi level pinned to that of the second semiconductor layer. By thus constructing an FET or the semiconductor device, an inversion or accumulation layer can be easily formed in the interface merely by applying a voltage to the control means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.