Instruction address calculation unit for a microprocessor
US4698747A · kind A · utility
5Cited by
1References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1985 |
| Grant date | Oct 6, 1987 |
| Priority date | — |
| Expiry date | Jun 28, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An execution unit for a microprocessor comprising a first section for performing arithmetic and logic operations on data, a second section for performing arithmetic operations on data memory addresses, and a third section for performing arithmetic operations on instruction addresses is disclosed in which data addresses and instruction addresses may be simultaneously calculated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.