Method of optimizing signal timing delays and power consumption in LSI circuits
US4698760A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1985 |
| Grant date | Oct 6, 1987 |
| Priority date | — |
| Expiry date | Jun 6, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of optimizing signal timing delays and power consumption through multi-path LSI circuits constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of power levels which are selectable to control the timing delays through the circuit block, wherein the method steps include the formation of a power-performance derivative for each circuit block, identifying therefrom the relative contribution to signal delay of the circuit block in the entire multi-path configuration, and selecting the optimum power level for an overall multi-path minimum signal delay condition, through a process of iterative calculation of timing delays through individual circuit blocks and multi-path timing analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.