Delay circuit for gate-array LSI
US4700089A · kind A · utility
348Cited by
9References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1985 |
| Grant date | Oct 13, 1987 |
| Priority date | — |
| Expiry date | Aug 20, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit for a gate-array LSI including at least one inverter having a plurality of P-channel transistors (Q.sub.1p to Q.sub.4p) and a plurality of N-channel transistors (Q.sub.1n to Q.sub.4n) connected in series. The P-channel/N-channel transistors are driven by an input potential (IN), and the common output of the innermost pair of P-channel/N-channel transistors generates an output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.