Semiconductor integrated circuit device and method of producing the same
US4701349A · kind A · utility
52Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1985 |
| Grant date | Oct 20, 1987 |
| Priority date | — |
| Expiry date | Dec 9, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicide layer of a refractory metal for reducing resistance and a nitride layer for preventing diffusion of aluminum are formed on the source and drain regions of an MISFET. The silicide layer is formed in self-alignment with the source and drain regions by two annealings effected at a low temperature and at a high temperature, respectively, and has a low resistance. The nitride layer is formed by directly nitriding the silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.