Pixel defect correction apparatus
US4701784A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1986 |
| Grant date | Oct 20, 1987 |
| Priority date | — |
| Expiry date | Jan 31, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/68
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A defect correction apparatus includes a memory having information of image failure of a solid state imaging device, a coincidence detection circuit for detecting a position of pixel having a failure at the time of image pick up, and a failure correction circuit. The failure correction circuit includes structure for producing plural signals for correction of signals of pixels around the pixel having the failure, and structure for selecting an optimum one from the produced plural signals, for correction responding to condition of the image and signals of the pixel therearound, and to use the selected optimum signal for correction by switching for the signal of the failure pixel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.