Method and a circuit arrangement for digital signal processing utilizing adaptive transversal filter techniques
US4701873A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 1984 |
| Grant date | Oct 20, 1987 |
| Priority date | — |
| Expiry date | Dec 14, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03038
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
For digital signal processing with a transversal filter having a (N-1) stage delay chain which is fed at its input with the digital signal to be processed and is provided with taps, subsum signals are stored which correspond to the N/w consecutive groups of, in each case A.sup.w possible combinations of, in each case, w consecutive, A-value tapped signal elements, where the subsum signals are formed from tapped signal elements which are each assigned to a group and are evaluated in accordance with the relevant filter setting. During each delay stage, in accordance with the relevant N/w actual combinations tapped elements, the associated subsum signals are successively read from a memory and added to one another to form an output signal element. The subsum signals can be iteratively formed in that each of the successively-read subsum signals, combined with a correction value, forms a corrected subsum signal which is stored in place of the read subsum signal as a new subsum signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.