Digital signal processing apparatus
US4701874A · kind A · utility
6Cited by
8References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1983 |
| Grant date | Oct 20, 1987 |
| Priority date | — |
| Expiry date | Dec 12, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital signal processing apparatus is disclosed. A delay circuit generates (2p+1) signals x.sub.k-n to x.sub.k+n (n=0, 1, 2, . . . , p), each having a difference respective delay time. The apparatus further comprises a computation circuit responsive to the foregoing signal for computing ##EQU1## wherein coefficients j and h.sub.0 to h.sub.n are ".+-.1" and "1" or "0", respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.