Highspeed parallel adder with clocked switching circuits
US4701877A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1984 |
| Grant date | Oct 20, 1987 |
| Priority date | — |
| Expiry date | Nov 27, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3876
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a parallel adder circuit, first and second full adders each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal are alternately connected such that the carry output terminal of the preceding full adder is directly connected to the carry input terminal of the succeeding full adder. In order to shorten the carry propagation delay time, the first full adder is arranged to receive an inverted carry signal (FALSE) from the preceding stage and to provide a carry signal (TRUE) to the succeeding stage, while the second full adder is arranged to receive a carry signal (TRUE) from the preceding stage and to provide an inverted carry signal (FALSE) to the succeeding stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.