Built-in self-test system for VLSI circuit chips
US4701920A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1985 |
| Grant date | Oct 20, 1987 |
| Priority date | — |
| Expiry date | Nov 8, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved built-in self-test system fabricated on an LSI circuit chip for performing dynamic tests of main logic function operation. The built-in self-test system includes a control register comprising a series of static flip-flops connected for serial test data transfer and for producing test system control signals. An input shift register connected for serial test data transfer with the control register and for parallel test data transfer with the main logic function is formed by a series arrangement of static flip-flops. An output register connected for serial test data transfer with the input register, and for parallel test data transfer with the main logic function, is formed by a series arrangement of static flip-flops. A test clock enable signal is latched by a test clock enable latch, and gated with a system clock signal to produce input and output register clock signals. A test strobe signal is latched by a test strobe latch and strobed by a flip-flop for use as a control register enable signal. The latched test strobe signal and the latched test clock enable signal are gated with the system clock signal for use as a control register clock signal. A test data output mult…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.