Non-restricted level shifter
US4703199A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 3, 1985 |
| Grant date | Oct 27, 1987 |
| Priority date | — |
| Expiry date | Apr 3, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high frequency CMOS voltage level shifter providing either an inverted or noninverted signal output shifted in voltage level from an input signal. The level shifter includes two pairs of metal oxide semiconductor transistors with the transistors of each pair connected together and respectively connected to a first and second voltage source. The gates of a transistor in each pair are cross connected to the interconnected drains of the opposing transistor pair. First and second conducting elements are respectively connected to the cross connected transistor gates to discharge a transient capacitive gate charge present during output signal voltage level shifting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.