Static bistable flip-flop circuit obtained by utilizing CMOS technology
US4703200A · kind A · utility
18Cited by
4References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 25, 1986 |
| Grant date | Oct 27, 1987 |
| Priority date | — |
| Expiry date | Feb 25, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A static bistable flip-flop circuit using CMOS technology. The flip-flop reduces the number of CMOS transistors by not using two complimentary transistors in parallel for certain switches. This reduces the risk of transparency which is inherent with conventional CMOS complimentary transistors. Between the input and output of the circuit there is only a first N channel transistor, a first inverter, a second N channel transistor and a second inverter connected in series.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.