Ready line synchronization circuit for use in a duplicated computer system
US4703421A · kind A · utility
67Cited by
6References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 1986 |
| Grant date | Oct 27, 1987 |
| Priority date | — |
| Expiry date | Jan 3, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronizing circuit synchronizes the asynchronous ready signals for two separate microprocessor subsystems that are running synchronously as part of a fault tolerant computer system. Duplicated synchronization circuits, confined in a master-slave arrangement, are utilized with the duplicate microprocessors. Storage and gating circuitry are used to provide the precise timing signals required for such synchronization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.