Method and apparatus for computing and implementing error detection check bytes
US4703485A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 10, 1986 |
| Grant date | Oct 27, 1987 |
| Priority date | — |
| Expiry date | Feb 10, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Improved design, computation and implementation of pairs of error detection check bytes, where such bytes are appended to the end of a variable length record for data integrity check of the entire record after ECC correction, is provided. The error detection check bytes are each computed using different powers of the same companion T matrix of a degree-eight primitive polynomial used for computing associated ECC check bytes. Use of the same T matrix provides the computational convenience of a reasonable size Galois field of GF(2.sup.8), while providing long cycle length through a recurring offset within the data sequences corresponding to two members of each pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.