Microelectronic package
US4705917A · kind A · utility
80Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1985 |
| Grant date | Nov 10, 1987 |
| Priority date | — |
| Expiry date | Aug 27, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package for the protection, housing, cooling and interconnection of a microelectronic chip. The package is made of a plurality of ceramic layers, each of which carries a particular electrically conductive pattern and which have interior openings therein so as to provide recesses in which the chip and discrete capacitors can be located and connected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.