Differential amplifier having ratioed load devices
US4706036A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 1986 |
| Grant date | Nov 10, 1987 |
| Priority date | — |
| Expiry date | Dec 22, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45676
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential amplifier is provided which has a low systematic offset voltage and a small variation in quiescent current with respect to variations in processing and temperature while providing low input referred noise and good output drive capability. Each transistor of a differential input pair of transistors is coupled to a plurality of series-connected transistors which are fabricated with substantially equal control electrode dimensions to form composite load tranistors. An output stage having conventional source and sink transistors is coupled to the differential pair of transistors. The sink transistor is implemented as a composite transistor by a plurality of parallel-connected transistors, each also having substantially the same control electrode dimension. Since all the ratioed transistors have equal control electrode dimensions, variations over processing and temperature are minimized. The composite load transistors have a large effective gate length for low input referred noise, and the composite transistor of the output stage has a small effective gate length to provide good drive capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.