Complementary cascoded logic circuit
US4709166A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 1986 |
| Grant date | Nov 24, 1987 |
| Priority date | — |
| Expiry date | May 22, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/082
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a Complementary Cascoded Logic (C.sup.2 L) Circuit which performs the AND-INVERT (AI) (or NAND) function. The AND function is implemented with input PNP transistors and the invert function is implemented with a first NPN transistor. An inverted NPN transistor serves as a current source for the first NPN. A first low voltage Schottky diode is serially connected between the emitter of the first NPN transistor and the emitter of the inverted NPN current source transistor. The first Schottky diode precludes, under certain conditions, simultaneous conduction of the first NPN transistor and the inverted transistor. Oppositely poled second and third low voltage Schottky diodes are utilized via an emitter follower output to provide an output voltage swing of V.sub.R .+-.V.sub.F, where V.sub.R is a reference voltage and V.sub.F is the potential drop across a Schottky diode. The low power high speed logic circuit (C.sup.2 L) has particular utility in redundant circuit applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.