Subnanosecond programmable phase shifter for a high frequency digital PLL
US4709170A · kind A · utility
12Cited by
6References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 19, 1986 |
| Grant date | Nov 24, 1987 |
| Priority date | — |
| Expiry date | Nov 19, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00182
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for producing a programmable phase shift of clock pulses in response to the data on a group of control lines. The circuit includes a ramp generator stage coupled to drive a comparator stage which has a reference potential input determined by the control line data. The phase shift can be employed to produce a series of subnanosecond delay increments on the clock pulses and is useful in the fine adjustment of a digital phase lock loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.