General locking/synchronization facility with canonical states and mapping of processors
US4709326A · kind A · utility
22Cited by
5References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1984 |
| Grant date | Nov 24, 1987 |
| Priority date | — |
| Expiry date | Jun 29, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The transition table size and table-driven locking facilities if reduced by decomposing lock states into canonical states and canonical-actual maps, mapping actual processors to canonical processors, looking up a transition in a table which contains a new canonical state, notify bits and a canonical-canonical map, permuting the canonical-actual map using the canonical-canonical map, and permuting the notify bits using the original canonical-actual map.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.