Computer assisted fault isolation in circuit board testing
US4709366A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1985 |
| Grant date | Nov 24, 1987 |
| Priority date | — |
| Expiry date | Jul 29, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S706/916
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuit faults in an electronic system are isolated by a programmed computer that guides a technician node-by-node on a unit under test (UUT), such as a circuit board, to the source of a failure. Stimulus pattern signals are applied to the circuit, and responses at the circuit nodes are made by a measurement probe under the hand of the technician. As each node is probed, a stimulus pattern signal tailored for testing that node is applied to the UUT. The measured response is compared to a predetermined response corresponding to an operational UUT to generate a failure accusation or recommend the next node to be probed. The computer is programmed to expedite the search for the source of the failure by displaying to the technician clues which define the circuit nodes most apt to be defective as a result of preliminary functional testing of the UUT. The computer is further programmed to have a form of "intuition" whereby the particular nodes recommended for probing are determined in part by prior testing of the same type of UUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.