Method for forming latch-up immune, multiple retrograde well high density CMOS FET
US4710477A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1986 |
| Grant date | Dec 1, 1987 |
| Priority date | — |
| Expiry date | Aug 20, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/904
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high density CMOS device structure that is essentially immune to latch-up, and a method of fabricating the structure, is described. This is obtained by providing a well region within and adjacent a surface of a substrate, the well region having a multiple retrograde doping density profile, and by providing source and drain regions within the well and adjacent the surface of the substrate, the source and drain regions having associated therewith a greater than average density of residual defects within said well region, the greater density of residual defects being generally associated with the deepest portions of the source and drain regions and the immediately underlying portions of said well region, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.