Differential CMOS comparator for switched capacitor applications
US4710724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1986 |
| Grant date | Dec 1, 1987 |
| Priority date | — |
| Expiry date | Apr 2, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/302
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential input circuit for a switched capacitor CMOS voltage comparator is provided which minimizes offset voltages by configuring the load devices to utilize a single switched capacitor biasing network initialized from internally-generated bias voltages, while configuring the initialization switches for the differential input devices to also utilize internally-generated bias voltages such that the offset voltages are stored on the input capacitors. The power supply rejection performance of the voltage comparator is also optimized by connecting parallel load devices of opposite switching topology such that the same input impedance is seen at both load terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.