Data clock oscillator having accurate duty cycle
US4710730A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 1987 |
| Grant date | Dec 1, 1987 |
| Priority date | — |
| Expiry date | Mar 20, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B2200/0012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS data clock oscillator circuit is disclosed which provides a simple, inexpensive, high-specification oscillator with an accurate duty cycle. The data clock oscillator 100 includes an oscillator stage 121 providing an AC output signal having an average DC value determined by an applied bias voltage, a limiting stage 124 having MOSFETs 102 and 103 configured to form a back-to-back limiter network to limit the amplitude of the AC output signal, a CMOS biasing stage 122 including complementary MOSFETs 104 and 105 configured to form an active resistor voltage divider network providing the bias voltage for the oscillator stage, and a CMOS buffer stage 123 including complementary MOSFETs 106 and 107 configured to form an inverting amplifier network having a predefined input switching threshold. Buffer stage MOSFETs 106 and 107 have conduction types, geometries, and device parameters matched to those of bias stage MOSFETs 104 and 105, respectively. In this way the inverter network input switching threshold tracks the bias voltage over changes in temperature, supply voltage, and manufacturing process tolerances. The instant invention is particularly well adapted for use as a data cloc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.