Sequential decoding device for decoding systematic code
US4710746A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 1987 |
| Grant date | Dec 1, 1987 |
| Priority date | — |
| Expiry date | Feb 6, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/39
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sequential decoding device for decoding a data expressed by a systematic code having a symbol memory, a maximum likelihood path decision circuit, and a path memory, includes: an overflow detection circuit for detecting an overflow of the symbol memory, and a switch for supplying signal bit data, as an decoded output, read from the symbol memory directly to the path memory in correspondence with an overflow detection signal from the overflow detection circuit. The device includes further a path metric value increase/decrease monitoring circuit for monitoring the increase/decrease of a path metric value delivered from the maximum likelihood path decision circuit and controlling the switch in such a manner that, when a monotonous increase of path metric value is detected, the decoded output of the maximum likelihood path decision circuit is supplied to the path memory instead of a direct supply of the decoded output of the symbol memory to the path memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.