Interconnect scheme for shared memory local networks
US4710868A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1984 |
| Grant date | Dec 1, 1987 |
| Priority date | — |
| Expiry date | Jun 29, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1663
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of intelligent work stations are provided access to a shared memory through a switching hierarchy including a first array of mapping boxes for receiving a first address from an intelligent work station and including a virtual address and offset and for converting the virtual address into a terminal switch port designation and logical address, a first switch for forwarding the logical address and offset to the designated terminal switch port, a second array of mapping boxes for receiving the logical address and offset and for converting the logical address into a memory switch port designation and physical address, and a second switch for forwarding the physical address and offset to the designated memory switch port as an address to the shared memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.