Electronic postage meter having a nonvolatile memory selection means
US4710882A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 1985 |
| Grant date | Dec 1, 1987 |
| Priority date | — |
| Expiry date | Mar 12, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07B2017/00411
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An electronic postage meter having an improved memory selection circuit is disclosed. A custom memory map decoder circuit with resolution down to a single byte location is used to provide selection enabling signals to insure the selection of an appropriate device only when the addresses appropriate to that device are communicated. In accordance with the invention, at least two nonvolatile memories are provided. Writing to either of these nonvolatile memories is inhibited unless one and only one memory is selected. The circuit also prevents the selection of either of the nonvolatile memories in the event that the write strobe signal to the memories is held active.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.