Method of fabricating a self-aligned metal-semiconductor FET having an insulator spacer
US4711858A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1986 |
| Grant date | Dec 8, 1987 |
| Priority date | — |
| Expiry date | Jun 18, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/969
Abstract
A method for the fabrication of self-aligned MESFET structures with a recessed refractory submicron gate. After channel formation on a semi-insulating (SI) substrate, which may consist of a III-V compound semiconductor such as GaAs, with subsequent annealing, refractory gate material is deposited and patterned. This is followed by the overgrowth of a highly doped contact layer of, e.g., GaAs, using MOCVD of MBE processes resulting in poly-crystalline material over the gate "mask" and mono-crystalline material on exposed semiconductor surfaces. Next, the poly-crystalline material is removed in a selective etch process, this step being followed by the deposition of source and drain electrodes. In order to further improve process reliability, insulating sidewalls are provided at the vertical edges of the gate to avoid source-gate and drain-gate shorts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.