Buffered FET logic gate using depletion-mode MESFET's.
US4712023A · kind A · utility
14Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1986 |
| Grant date | Dec 8, 1987 |
| Priority date | — |
| Expiry date | Nov 13, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffered FET logic gate circuit has a bias diode (9), which is connected across the gate and the source of a current source FET (4) of a buffer part (3, 4), and a capacitor (8), which is connected across the gate of said FET (4) and an input terminal (V.sub.I); and thereby a high load drivability with a low power consumption rate is realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.