Self-timed random access memory chip
US4712190A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1985 |
| Grant date | Dec 8, 1987 |
| Priority date | — |
| Expiry date | Jan 25, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-timed random access memory circuit is designed on a single monolithic integrated circuit chip. The chip includes a random access memory including addressable storage locations, address decoding circuitry, data input and output circuitry and write enable circuitry. In addition, the chip includes input latches connected to chip input terminals which store data, address and operation control signals from off-chip circuitry in response to a timing signal, also from the off-chip circuitry. Also in response to the timing signal, an output latch on the chip stores data from the random access memory for transmission to output terminals, where the data is available to the off-chip circuitry. The input and output latches permit the self-timed random access memory circuit to perform in a pipelined manner. In addition, the chip includes circuitry that generates the control signals, in response to the latched control signals, with the correct timing for controlling the random access memory, obviating the necessity of the system designer designing a system including the chip having to design off-chip control circuitry with the required timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.