Method and device for correcting errors in memories
US4712216A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 1985 |
| Grant date | Dec 8, 1987 |
| Priority date | — |
| Expiry date | Oct 18, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The bit configurations are arranged in M-bit code words, each word comprising a number D of data bits and an even number N of error correcting bits. The data bits are partitioned into N fields with an error correcting bit associated with each field to indicate the parity of the associated field. The assignment of data bits to the N fields in such that, when the N fields are used to generate an N-bit error syndrome, this syndrome will contain an odd number n1 of bits at a first value if there is a single bit in error, where N-n1=n2 is also odd, and an even number of bits different from N to indicate a two-bit error. The number of bits of the first value are then used to determine whether the codeword is in its true or inverted form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.