Phase synchronization circuit
US4713621A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1985 |
| Grant date | Dec 15, 1987 |
| Priority date | — |
| Expiry date | Mar 28, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase synchronization circuit for controlling a graphic display device in a teletext receiving system. The phase synchronization circuit includes a delay circuit, adapted to delay in sequence clock signals which are to be phase-synchronized with a reference signal and to produce in sequence delayed clock signals, and a selection circuit, including set/reset circuits and gates, each gate receiving the output of the set/reset circuits and of the delayed clock signals. Among the delay clock signals, the signal that has the nearest edge timing to the edge of external signals is selected. The phase synchronization circuit has a short pull-in time and high-speed synchronization, is suitable for circuit integration, and offers improved reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.