Printed circuit board fault location system
US4714875A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1985 |
| Grant date | Dec 22, 1987 |
| Priority date | — |
| Expiry date | Apr 12, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/277
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An in-circuit testing apparatus (manufacturing defects analyzer) for the determination of manufacturing defects in an electrical circuit board such as short circuits, tracking faults, mininserted omitted and out-of tolerance components etc., and not for effecting full functional testing of the circuit board, comprises an array of bidirectionally current conducting analog switching networks each of which defines a test point for connection to a node of a circuit board and connectable, under software control of the respective switchng network, either to a stimulus source or to a reference (e.g. ground) potential and simultaneously also to an input of a measurement facility. A resistor, capacitor, inductor or other circuit component can be connected between the test points defined by two of the switching networks and can thus be subjected to an appropriate stimulus and its response measured and analyzed for determining the viability of the respective component. A modified form of the apparatus enables the gain of discrete transistors also to be monitored. A desk-top form of the apparatus has a recess in its main housing for receiving an interchangeable board-probing module which is cu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.