Electronic clock tuning system
US4714924A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 1985 |
| Grant date | Dec 22, 1987 |
| Priority date | — |
| Expiry date | Dec 30, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic clock tuning system for a digital computer of the type including a plurality of major function circuit boards comprised of a plurality of gate arrays. A clock pulse train is produced by a master oscillator, and distributed to each major function circuit board by a master fanout. The clock pulse train is distributed throughout each major function circuit board by a local fanout. Each major function circuit board includes a plurality of electronic delay arrays, each of which distributes the clock pulse train to a group of gate arrays on the major function board, and delays the clock pulse train supplied to each gate array by one of a plurality of discrete delay periods. Each electronic delay array includes shift registers for serially receiving digital delay tuning codes and for producing digital delay select signals representative of discrete delay periods. Delay circuits on each electronic delay array are responsive to one of the shift registers, and delay the clock pulse trains supplied to the gate arrays by discrete delay periods represented by the digital delay select signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.