Method of and system for fast functional testing of random access memories
US4715034A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 1985 |
| Grant date | Dec 22, 1987 |
| Priority date | — |
| Expiry date | Mar 4, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Random bits are written successively into the cells of a random access memory (RAM) system, then complemented, through a first sequence of cell addresses distributed substantially uniformly throughout all the cells of the memory. Through an opposite address sequence, the contents of the cells are read and then complemented. Finally, through the initial sequence of cell addresses, the contents of the cells are again read. Differences between read and expected cell contents identify memory cell faults. The random bits preferably are generated by a softward implemented, reversible pseudorandom sequence generator, and the uniform address sequence is generated by an address hasher programmed with an address function that exercises all address lines essentially equally.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.