Frequency divide by N circuit
US4715052A · kind A · utility
9Cited by
6References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 10, 1986 |
| Grant date | Dec 22, 1987 |
| Priority date | — |
| Expiry date | Mar 10, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/483
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divide by n circuit, where n is an odd number, which includes means for splitting an incoming clock signal of frequency "f" into two non-overlapping complementary clock signals of frequency "f" and a shift register circuit. The shift register circuit is coupled to the signal splitting means and generates an output clock signal of frequency f/n in response to the two complementary clock signals. The output clock signal has a duty cycle equal to ((n-1)/2+D.sub.in)/n where D.sub.in is the duty cycle of the incoming clock signal. The output duty cycle is substantially independent of processing and operating conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.