Peripheral controller for coupling data buses having different protocol and transfer rates
US4716525A · kind A · utility
60Cited by
3References
3Claims
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Key dates
| Filing date | Apr 15, 1985 |
| Grant date | Dec 29, 1987 |
| Priority date | — |
| Expiry date | Apr 15, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral controller is provided for controlling data transfers between peripheral devices operably on one type of data bus to devices operable on a second data bus. An intermediate buffer is utilized so that data is read into one memory block from the sending data bus and read out of another memory block to the receiving data bus. Controls are provided to prevent overwriting data which has not been transmitted and to prevent data transfers from the buffer until at least one block of memory has been filed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.