Output circuit having transistor monitor for matching output impedance to load impedance
US4719369A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1986 |
| Grant date | Jan 12, 1988 |
| Priority date | — |
| Expiry date | Aug 7, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output circuit comprises an output transistor circuit for applying an output signal to a transmission line connected to an output terminal, a circuit for driving the output transistor circuit in response to an input signal applied to an input terminal, and a control circuit by which the signal amplitude of a first wave applicable to the transmission line with a load connected to the output terminal through the transmission line is rendered approximately one half of the output signal amplitude with a load directly connected to the output terminal. The control circuit includes a monitoring transistor within the same chip as the output transistor circuit, a selected one of the output resistance and input signal of the output transistor circuit being controlled in accordance with the magnitude of the drain current of the monitoring transistor to adjust the amplitude of the signal applied to the transmission line. Transmission with transmitting and receiving ends having a well-defined transmission waveform is obtained, thereby making possible high-speed signal transmission between LSI chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.