Gate circuit of combined field-effect and bipolar transistors
US4719373A · kind A · utility
26Cited by
8References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1987 |
| Grant date | Jan 12, 1988 |
| Priority date | — |
| Expiry date | Apr 30, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.