Defect leakage screen system
US4719418A · kind A · utility
12Cited by
9References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1985 |
| Grant date | Jan 12, 1988 |
| Priority date | — |
| Expiry date | Feb 19, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit or system is provided wherein data is stored in circuits or cells of an array or matrix with the use of conventional or normal operating voltages. Voltages at internal nodes of the circuits or cells are altered to magnitudes beyond the normal operating ranges, which includes significantly decreasing the offset voltage, for a short period of time and then the stored data is read out at normal voltages and currents and compared with the data written into the circuits or cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.