Memory with improved column access
US4719602A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1985 |
| Grant date | Jan 12, 1988 |
| Priority date | — |
| Expiry date | Feb 7, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having an improved system for randomly accessing a preselected set of memory locations. The invention includes a set of "secondary sense amplifiers" which act as a high speed buffer between the memory's normal sense amplifiers and the memory's data input and output buffers. The secondary sense amplifiers are connected to selected ones of the sense amplifiers in accordance with a first predefined subset of the memory's column address signals. A decoder circuit, which is directly responsive to a second predefined subset of the column address signals, selects one of the secondary sense amplifiers and connects it to the memory's data input and output buffers. Since the decoder is directly responsive to the second predefined subset of the column address signals and does not need to latch in new address values after the detection of an address signal transition, all the secondary sense amplifiers can be accessed much faster than the other data storage locations in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.